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countqi
- 计数器 同步异步预置数清零 verilog hdl 编写-Asynchrony preset counter reset the Verilog HDL few prepared
mod6_cnt
- 一个用VerilogHDL语言编写的模6的二进制计数器-a Verilog HDL language used in the preparation of the six-binary counter
9.3_Pulse_Counter
- 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 9.3.1 脉冲计数器的工作原理 9.3.2 计数模块的设计与实现 9.3.3 parameter的使用方法 9.3.4 repeat循环语句的使用方法 9.3.5 系统函数$random的使用方法 9.3.6 脉冲计数器的Verilog-HDL描述 9.3.7 特定脉冲序列的发生 9.3.8 脉冲计数器的硬件实现 -based on V
数据结构c描述习题集答案
- 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能,可以进行自增和自减计数,其计数周期为2^N(N为二进制位数)。 二、设计原理 输入/输出说明: d:异步置数数据输入; q:当前计数器数据输出; clock:时钟脉冲; count_en:计数器计数使能控制(1:计数/0:停止计数); updown:计数器进行自加/自减运算控制(1:自加/0:自减); load_d-a counter a reduction, design requirem
在ISE下调用计数器IP核
- 非常简单的计数器,在ISE下调用计数器IP核,使用verilog开发得到的。-Very simple counter, under the invocation counter in the ISE IP cores, development has been the use verilog.
Example-b3-1
- UART串口加法计数器的使用,用verilog语言编写 -the use of UART serial addition counter
verilog1
- 用verilog语言编写的6分频分频计数器。分频后用来控制蜂鸣器响,也可以修改代码做成更高分频的计数器。压缩包内也包含此分频器的modelsim仿真文件-Verilog language with 6 frequency divider counter. Frequency and used to control the buzzer sound, you can modify the code to make a higher frequency counter. Compressed pac
RISC-CPU
- 用FPGA实现一个简易的CPU,采用精简指令集结构,每一条指令有16bit,高三位为指令操作数,后13位为地址,该CPU能实现8种指令操作,分别有HLT(空一个中期)ADD(相加操作)SKZ(为零跳过)AND(相与操作)XOR(异或操作)LDA(读数据)STO(写数据)JMP(无条件跳转指令)。cpu包括8个部件,分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器,各个部件之间的相互操作关系由状态控制器来控制,程序指令存放在初始rom中,本例程存放
devider_design
- Abstract循序电路第一个应用是拿来做计数器((笔记) 如何设计计数器? (SOC) (Verilog) (MegaCore)),有了计数器的基础后,就可以拿计数器来设计除频器,最后希望能做出能除N的万用除频器。-Abstract The first application of sequential circuits are used to make counter ((notes) How to design a counter? (SOC) (Verilog) (MegaCore)),
counter16
- 一个verilog源代码,作用是计数器的建模。-A verilog source code, the role of the counter model.
fb
- 占空比为1:1 的方波verilog程序,通过修改counter可以改变频率及占空比-1:1 duty cycle square wave of verilog procedures, counter can be changed by modifying the frequency and duty cycle
clock10
- 篮球24秒计数器。用Verilog语言编写,在maxplus2中编译运行。适用于大部分FPGA开发板,但必须更改引脚分配。-24 seconds counter basketball. Verilog language used in compiling maxplus2 run. Applicable to most FPGA development board, but must change the pin assignment.
at7_ex03
- 使用FPGA内部的PLL产生时钟,计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
cntCode
- 通用计数器程序,便于初学者掌握verilog HDL语言的进行计数器设计原则(General counter program is easy for beginners to master the counter design principles of Verilog HDL language.)
密码锁
- 程序通过采集输入信息,与FPGA的存储值进行比较,如果密码正确,则开锁电路打开;如果密码错误,锁不打开,并且计数器进行+1操作;累计3次输入密码错误,给警报一个高电平,让其报警。(By collecting input information, the program compares with the storage value of FPGA. If the password is correct, the unlocked circuit opens; if the password is
计数器
- 计数器,可参数化的计数器,进行M模的计数操作。(Counter, parameterized counter, for M - mode counting operation)
contpulso
- A code use for doing a pulse counter in high in ms with output to display, which when pressing a button the count is displayed on the display and when the button is released it stops at a value, but if it is pressed again continue the count. It has a
counter
- 基于fpga的倒计时器。 可实现6位数的倒计时,通过按键设置初始值,倒计时结束提醒等功能(An inverted timer based on FPGA)
模24计数器
- 模24计数器的Quartus II文本输入设计及其test bench(Quartus II text input design and test bench of modulo 24 counter)
DPWM
- 用Verilog实现数字脉宽调制模块,主要模块有锁相环、计数器、多路选择器(The digital pulse width modulation module is realized by Verilog. The main modules are PLL, counter and multiplexer)